TESIC-SC Dual-interface Secure Chips

Applications

  • TESIC-SC  is a family of flash-based dual-interface secure microcontroller  chips for banking payment, open loop transit fare and e-government documents

Features

Secure asynchronous CPU

  • 16/32-bit microcontroller

Memories

  • Low-power flash memory, organized in a dual-bank system (one bank for code, one bank for data), allowing concurrent read-read and read-write access to both banks
  • RAM, with one bank dedicated to the CPU and one bank accessible by both the CPU and the public key crypto-coprocessor
  • ROM, including boot strap

Interfaces

  • ISO/IEC 14443 type A contactless interface
  • ISO/IEC 7816 contact interface

Secure high-performance asynchronous crypto-coprocessors

  • DES/3DES crypto-coprocessor: supports data of 64 bits, 2 or 3 keys of 64 or 128 bits, ECB and CBC modes in HW; compliant with FIPS 46-3; single-DES can be executed in less than 1 μs, triple-DES in less than 3 μs
  • AES crypto-coprocessor: supports data of 128 bits, keys of 128, 192 or 256 bits, ECB mode in HW; optimized for CBC mode in SW ; compliant with FIPS 197; AES with 128-bit key can be executed in less than 8 μs
  • RSA and ECC public key crypto-coprocessor: supports data and keys up to 4096 bits; supports the following operations in HW: bitwise exclusive or, bitwise and, addition, subtraction, copy, left shift, right shift, multiplication, Montgomery multiplication, exponentiation, sliding windows, exponentiation with Montgomery ladder; RSA CRT 1024 can be executed in less than 17 ms
  • CRC: 16-bit, compliant with ISO/IEC 13239
  • TRNG: compliant with AIS-31/FIPS140-2

Security sensors 

Certification

  • EMVCo, CC EAL5+ (2016)

Advantages

  • Faster transaction time
  • Robustness in difficult environment

TESIC-SC Advantages

Due to the delay-insensitivity property of the technology used for the design of the TESIC core, TESIC-SC is able to continuously adapt/maximize its processing speed in real-time to whatever energy is coming from the card reader. This allows much higher card performance and reliability with card readers of lesser quality.

Product family

TESIC-SC-Dual-interface-Secure-Chips-Product-Family

Datasheets [download pdf]

Architecture TESIC-SC Dual-interface Secure Chips

Schema-Architecture-TESIC-SC-Dual-interface-Secure-Chips