Tiempo Secure is offering positions to junior digital hardware engineers to participate to innovative secure IP and chip designs.
Tiempo Secure develops and licenses secure element IP cores and secure software libraries that are guaranteed to enable Common Criteria EAL5+ or equivalent security certification of any System-on-Chip (SoC) or application processor chip integrating these cores. Supported applications are JavaCard 3.0.5 OS, integrated SIM, Web authentication, payment, smart car access and vehicle to anything communication, and their corresponding certifications GSMA, FIDO2, EMVCo and V2X HSM.
Full time position located near Grenoble, France.
Required experience
- Master degree or PhD in microelectronics
Responsible for
- Design and verification of digital blocks
- Chip-level integration
Must have skills
- RTL Verilog for hardware synthesis using standard tools (e.g., Synopsys DC)
- Functional Verilog and SystemVerilog for hardware verification using standard tools (e.g., Synopsys VCS, Siemens/Mentor QUESTA)
- Autonomous, able to understand a specification and to implement a hardware architecture
- Written and spoken English, capable to write documents in good English.
Nice to have skills
- Knowledge in cryptography
