Tiempo Secure is looking for a senior digital hardware engineer to participate to innovative secure IP and chip designs.
Tiempo Secure develops and licenses secure element IP cores and secure software libraries that are guaranteed to enable Common Criteria EAL5+ or equivalent security certification of any System-on-Chip (SoC) or application processor chip integrating these cores. Supported applications are JavaCard 3.0.5 OS, integrated SIM, Web authentication, payment, smart car access and vehicle to anything communication, and their corresponding certifications GSMA, FIDO2, EMVCo and V2X HSM.
Full time position located near Grenoble, France.
Required experience
- Six years minimum in hardware digital design
Responsible for
- Specification of design architectures to meet customer requirements
- Design and verification of digital blocks and chip-level integration
Must have skills
- RTL Verilog for hardware synthesis using standard tools (e.g., Synopsys DC)
- Functional Verilog and SystemVerilog for hardware verification using standard tools (e.g., Synopsys VCS, Siemens/Mentor QUESTA)
- Autonomous, capable to write specifications from customer requirements and to define hardware architecture
- Written and spoken English, capable to write documents in good English.
Nice to have skills
- DFT design experience
- RISC-V architecture
- Cryptography and security
