Tiempo Secure is looking for a senior verification engineer to participate to innovative secure IP and chip designs.
Tiempo Secure develops and licenses secure element IP cores and secure software libraries that are guaranteed to enable Common Criteria EAL5+ or equivalent security certification of any System-on-Chip (SoC) or application processor chip integrating these cores. Supported applications are JavaCard 3.0.5 OS, integrated SIM, Web authentication, payment, smart car access and vehicle to anything communication, and their corresponding certifications GSMA, FIDO2, EMVCo and V2X HSM.
Full time position located near Grenoble, France.
Required experience
- Five years minimum in IP and SoC verification
Responsible for
- Verification of digital IP and complete System-on-Chip
- Development of verification environments in SystemVerilog/UVM/other
Must have skills
- Functional Verilog and SystemVerilog for hardware verification using standard tools (e.g., Synopsys VCS, Mentor QUESTA)
- Good knowledge of VMM/UVM advanced methodologies
- Autonomous, capable to write verification plan based on implementation documentation
- Written and spoken English, capable to write documents in good English.
Nice to have skills
- DFT verification experience
- Verification UPF
- RISC-V architecture
- Cryptography and security
Tiempo Secure is looking for a senior verification engineer to participate to innovative secure IP and chip designs.
Tiempo Secure develops and licenses secure element IP cores and secure software libraries that are guaranteed to enable Common Criteria EAL5+ or equivalent security certification of any System-on-Chip (SoC) or application processor chip integrating these cores. Supported applications are JavaCard 3.0.5 OS, integrated SIM, Web authentication, payment, smart car access and vehicle to anything communication, and their corresponding certifications GSMA, FIDO2, EMVCo and V2X HSM.
Full time position located near Grenoble, France.
Required experience
- Five years minimum in IP and SoC verification
Responsible for
- Verification of digital IP and complete System-on-Chip
- Development of verification environments in SystemVerilog/UVM/other
Must have skills
- Functional Verilog and SystemVerilog for hardware verification using standard tools (e.g., Synopsys VCS, Mentor QUESTA)
- Good knowledge of VMM/UVM advanced methodologies
- Autonomous, capable to write verification plan based on implementation documentation
- Written and spoken English, capable to write documents in good English.
Nice to have skills
- DFT verification experience
- Verification UPF
- RISC-V architecture
- Cryptography and security
