Tiempo Secure announces TESIC RISC-V Secure Element IP and development kit

Building upon its longstanding expertise in semiconductor design, Tiempo Secure is proud to announce its TESIC RISC-V Secure Element IP, which brings an unprecedented level of security to embedded systems, it is certification-ready for Common Criteria EAL 5+ level, and makes SoC development easy thanks to its integration with the complete RISC-V ecosystem. Tiempo Secure […]

Tiempo Secure becomes a Strategic Member of RISC-V International

As a Strategic member of RISC-V International, Tiempo Secure will secure and integrate processors implementing the RISC-V open standard instruction set architecture (ISA) into its TESIC Secure Element IP, thus easing integration for its customers; in addition, Tiempo Secure will bring its recognized security expertise to the RISC-V community. Grenoble, France – October 11, 2022 – By becoming […]