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TESIC CC EAL5+ Secure Element Hard Macro

TESIC is a CC EAL5+ PP0084 proven/certification-ready secure element IP that is delivered as hard macro for plug-and-play System-on Chip (SoC) integration

Targeted designs are SoCs that require a security enclave highly protected against side-channel attacks and perturbation/fault attacks, and that execute secure software such as iSIM, EMVCo payment, FIDO2 Web authentication, V2X HSM protocol and/or other security routines for the SoC system, including secure boot, secure OTA firmware update, secure storage and secure debug.

TESIC includes a secure MCU, secure cryptographic processors and hardware accelerators, security sensors, secure memories and standard interfaces for easy integration and test. Memory sizes, cryptographic accelerators and interfaces can be customized according to customer requirements.

TESIC supports any non-volatile memory (NVM) architecture, including embedded flash and MRAM, and the use of any external flash chip. It implements a CC EAL5+ PP0084 compliant security protocol for the encrypted communication and secure storage with any external flash.

TESIC is delivered as a GDS hard macro to the certified fab, with the guarantee to pass CC EAL5+ PP0084 and/or EMVCo security certification of the chip integrating this macro. It is available on multiple silicon processes, including GF 55 LPx, TSMC 40 ULP, GF 22 FDX and TSMC 16 FFC.

CC EAL5+ secure microcontroller system

  • Secure microcontroller core
  • Secure memory Protection Unit (MPU)
  • Timers (3)

CC EAL5+ secure cryptography

  • FIPS 197 compliant AES up to 256 bits
  • FIPS 46-3 compliant DES/3DES with hardware CBC mode
  • Public Key Accelerator
    • ECC up to 521 bits
    • RSA up to 4096 bits,
  • SHA2 and SHA3 hardware accelerators
  • CRC 16-bit, compliant with ISO/IEC 13239
  • TRNG compliant with AIS-31 and FIPS140-2
  • PRNG

CC EAL5+ security sensors

  • Glitch detectors
  • Temperature sensor
  • Active shield
  • 4 phases hand-shake protocol

Interfaces

  • APB slave interface
  • AHB master interface
  • Secure GPIOs
  • Secured standard JTAG TAP for test
  • ISO 7816 slave interface for integration of SoC test framework

Option

  • NFC ISO 14443 for admin interface or payment
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