TESIC CC EAL5+ Secure Element Hard Macro

Targeted designs are SoCs that require a security enclave highly protected against side-channel attacks and perturbation/fault attacks, and that execute secure software such as iSIM, EMVCo payment, FIDO2 Web authentication, V2X HSM protocol and/or other security routines for the SoC system, including secure boot, secure OTA firmware update, secure storage and secure debug.

TESIC includes a secure MCU, secure cryptographic processors and hardware accelerators, security sensors, secure memories and standard interfaces for easy integration and test. Memory sizes, cryptographic accelerators and interfaces can be customized according to customer requirements.

TESIC supports any non-volatile memory (NVM) architecture, including embedded flash and MRAM, and the use of any external flash chip. It implements a CC EAL5+ PP0117 compliant security protocol for the encrypted communication and secure storage with any external flash.

TESIC is delivered as a GDS hard macro to the certified fab, with the guarantee to pass CC EAL5+ PP0117 and/or EMVCo security certification of the chip integrating this macro. It is available on multiple silicon processes, including GF 55 LPx, TSMC 40 ULP, GF 22 FDX and TSMC 16 FFC.