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Targeted designs are SoCs that require a security enclave highly protected against side-channel attacks and perturbation/fault attacks, and that execute secure software such as iSIM, EMVCo payment, FIDO2 Web authentication, V2X HSM protocol and/or other security routines for the SoC system, including secure boot, secure OTA firmware update, secure storage and secure debug.
TESIC includes a secure 32-bit RISC-V microprocessor core, secure cryptographic processors and hardware accelerators, security sensors, secure memories and standard interfaces for easy integration and test. Memory sizes, cryptographic accelerators and interfaces can be customized according to customer requirements.
TESIC supports any non-volatile memory (NVM) architecture, including embedded flash and MRAM, and the use of any external flash chip. It implements a CC EAL5+ PP0117 compliant security protocol for the encrypted communication and secure storage with any external flash.
TESIC is delivered as soft IP (RTL and netlist files) to CC compliant design centers, with additional secure design services offered by Tiempo Secure to ensure future CC EAL5+ or other security certification, or as a GDS hard macro to the certified fab, with the guarantee to pass CC EAL5+ PP0117 and/or EMVCo security certification of the chip integrating this macro. It is available on multiple silicon processes, including GF 55 LPx, TSMC 40 ULP, GF 22 FDX and TSMC 16 FFC.
TESIC Web Authentication enables highly secure, encrypted, anonymous, and completely password-free logins as well as digital signing
TESIC V2X HSM enables vehicles and road-signs to communicate securely with each other’s in order to avoid accidents and create smoother traffic flows
Software Development Kit (TESIC-SDK), CC EAL5+ certified secure boot loader (TESIC-AdminLoader), CC EAL5+ certified secure cryptographic library (TESIC-CryptoLib), secure external storage manager (TESIC-ESM), and TESIC Security Toolbox (TESIC-TBX)